The present invention generally relates to semiconductor devices and methods of producing the same, and more particularly to a semiconductor device which is resin encapsulated and to a method of producing such a resin encapsulated semiconductor device.
Recently, although the size of the semiconductor chip of the resin encapsulated semiconductor device has increased, there are demands to reduce the side of the package itself. However, in the existing semiconductor device which uses the lead frame having the two-dimensional structure, there is a limit to reducing the size of the package. Furthermore, when the size of the package is reduced to the limit, there are problems in that the mechanical strength, reliability and the like of the semiconductor device deteriorate.
Accordingly, there are proposals to use the top or bottom surface of the semiconductor chip which was conventionally unused by arranging the leads, selectively, on the top or bottom surface of the semiconductor chip, so that the leads have a three-dimensional structure. The COL (Chip on Lead) and the LOC (Lead on Chip) are examples of such a three-dimensional structure, and a Japanese Laid-Open Patent Application No. 61-218139 proposes such a three-dimensional structure.
FIGS. 1(-A) and 1(B) show an example of a conventional semiconductor device having the COL structure. FIG. 1(A) shows a plan view of the semiconductor device with a part of an encapsulating resin omitted, and FIG. 1(B) shows a front view of the semiconductor device with a part of the encapsulating resin omitted.
In FIGS. 1(A) and 1(B), inner leads 4 are arranged in a predetermined shape, and a stepped part 4a is provided at a part where a semiconductor chip 1 is mounted. The semiconductor chip 1 is fixed above the inner leads 4 via an insulator 6. Electrodes of the semiconductor chip 1 and ends of the inner leads 4 are connected via bonding wires 3, and the entire semiconductor device, excluding the outer leads 5, is packaged by an encapsulating resin 2.
Hence, according to the COL structure, the inner leads 4 run on the lower side of the semiconductor chip 1 to form the package having the three-dimensional structure.
FIGS. 2(A) and 2(B) show an example of a conventional semiconductor device having the LOC structure. FIG. 2(A) shows a plan view of the semiconductor device with a part of the encapsulating resin omitted, and FIG. 2(B) shows a front view of the semiconductor device with a part of the encapsulating resin omitted. In FIGS. 2(A) and 2(B), those parts which are essentially the same as those corresponding parts in FIGS. 1(A) and 1(B) are designated by the same reference numerals, and a description thereof will be omitted.
In FIGS. 2(A) and 2(B), the insulator 6 is provided on the semiconductor chip 1, and the inner leads 4 are arranged on top of the insulator 6. The ends 4b of the inner leads 4 and the electrodes of the semiconductor chip 1 are connected via the bonding wires 3, and the entire semiconductor device, excluding the outer leads 5, is packaged by an encapsulating resin 2.
Hence, according to the LOC structure, the inner leads 4 run on the upper side of the semiconductor chip 1 to form the package having the three-dimensional structure.
However, according to the COL and LOC structures, the inner leads 4 run only on the lower or upper side of the semiconductor chip 1, and this arrangement is insufficient for efficiently providing the necessary wiring for a more complex circuit.
In addition, the insulator 6 must be provided between the semiconductor chip 1 and the inner leads 4. If the matching of this insulator 6 and the encapsulating resin 2 is poor or the adhesion between the insulator 6 and the encapsulating resin 2 is insufficient, there is a problem in that a crack is easily formed in the encapsulating resin 2 after the packaging. If such a crack is formed in the encapsulating resin 2, the reliability of the semiconductor device greatly deteriorates.
Furthermore, particularly in the case of the LOC structure, the insulator 6 provided on the circuit forming surface of the semiconductor chip 1 is a thin insulator film, and the inner leads 4 arranged on this thin insulator film, is made of a metal having a large coefficient of linear expansion. For this reason, the inner leads 4 undergo a large expansion when the semiconductor device operates and the semiconductor chip 1 generates heat, and a large difference is introduced between the expansion of the semiconductor chip 1 and the expansion of the inner leads 4. A stress is generated at the surface of the semiconductor chip 1 due to this difference in the expansions, thereby applying forces on and deforming the circuits within the semiconductor chip 1.
An improved semiconductor device shown in FIG. 3 having the LOC structure was thus proposed in a Japanese Laid-Open Patent Application No. 59-66157 (Published Application No. 4-1503). In FIG. 3, (A) shows a cross-sectional side view of the semiconductor device, (B) shows a plan view of a lead frame, and (C) shows a plan view of a stage frame.
In FIGS. 3(A) to 3(C), a lead frame 8 includes inner leads 4 and outer leads 5 which are formed to predetermined shapes and connected to a frame 15. On the other hand, a stage frame 9 includes a rectangular stage 13 which is connected to a central position of the frame 15 via a bent part 10 which forms a step relative to the frame 15.
As shown in FIG. 3(A), the semiconductor chip 1 is mounted on the stage 13, and the packaging is made by the encapsulating resin 2 after overlapping (i.e., superposing) the lead frame 8 and the stage frame 9. In this state, the semiconductor chip 1 and the inner leads 4 are mutually separated by the provision of the bent part 10 in the stage frame 9. Accordingly, the semiconductor chip 1 and the inner leads 4 are isolated by the encapsulating resin 2 which exists therebetween. As a result, the problems caused by the provision of the insulator 6 in the semiconductor device shown in FIG. 2 are eliminated because the semiconductor device shown in FIG. 3 does not require the insulator 6.
However, because the bent part 10 for forming the gap between the semiconductor chip 1, which is mounted on the stage 13, and the inner leads 4 is provided inside the package, there is a new problem in that the size of the package cannot be made less than or equal to a sum of the size of the semiconductor chip 1 and the size of the bent part 10.